1. Field of the Invention
This invention relates generally to I/O processor based controllers, and more particularly to I/O chip hiding of processor based controllers from operating systems.
2. Description of the Related Art
The use of personal computers has expanded remarkably in recent years. Modern personal computers are generally characterized by a flexible hardware architecture and a relatively open software architecture. The use of standardized bus architectures (such as the PCI Bus and the Fibre Channel) has permitted users to customize their personal computers to meet their particular hardware and software needs. In consequence, a variety of input and output devices are available for most popular personal computers.
It is beneficial to have a large selection of reliable input/output (I/O) devices. The availability of such a wide range of input-output devices increases the size of the market of potential purchasers of such devices by providing the customization capabilities desired by a larger pool of potential purchasers. Furthermore, it is helpful for input-output devices to embody a greater degree of “intelligence.” Thus, for example, it would be desirable for each input-output device to be able to perform its function without needing active supervision or interaction with the central processing units (CPUs) of the computer system.
FIG. 1 is a block diagram showing an exemplary conventional computer motherboard 100 having an on-board small computer system interface (SCSI) controller. The computer motherboard 100 includes a central processing unit (CPU) 102 in communication with a peripheral component interconnect (PCI) bus 108. The PCI bus 108 is further in communication with a SCSI controller 104, system memory 106, and a SCSI hard drive 112 for persistent storage. In addition, the computer motherboard 100 includes a plurality of PCI connection ports 110, or “slots,” in communication with the PCI bus 108, for PCI based cards. PCI provides a high-speed data path between the CPU and peripheral devices (video, disk, network, etc.), and allows “plug and play” capability, automatically configuring the PCI cards at startup. Further, PCI allows interrupt requests (IRQs) to be shared. IRQs are used to signal the CPU 102 that a peripheral event has started or terminated. Thus, sharing of IRQs helps solve the problem of limited IRQs being available on a computer system. For example, if only one IRQ remains after industry standard architecture (ISA) devices are given their required IRQs, all PCI devices could share the remaining IRQ.
The SCSI controller 104 provides a hardware interface that allows for the connection of a plurality of peripheral devices. Typically, SCSI peripherals are daisy chained together using a second port for connecting to the next device in line. However, in the example of FIG. 1, the SCSI controller 104 controls a single hard drive 112.
To read a file from the hard drive 112, the CPU 102 transmits an interrupt signal to the SCSI controller 104 via IRQ line 114, and also provides a read command to the SCSI controller 104 using the PCI bus 108. In response, the SCSI controller 104 transmits a command to the SCSI hard drive 112 to access the particular disk sectors. When the SCSI hard drive 112 reports back, the SCSI controller 104 uses direct memory access (DMA) circuitry to transfer the data on the SCSI hard drive 112 directly to the system memory 106. The DMA circuitry is specialized circuitry that transfers data from memory to memory without using the CPU 102, which allows data to be transferred much faster than using the CPU 102 for every byte of transfer.
Once the transfer is complete, the SCSI controller 104 transmits an interrupt indicating the data is in memory to the CPU 102 via the IRQ line 114. Most input-output devices generate responses and initiate communications with the CPU 102 by generating an interrupt. Such an interrupt causes the CPU 102 to suspend execution of whatever task the CPU 102 is currently executing in order to respond to the I/O device generating the interrupt, in this case the SCSI controller 104. Thereafter, the CPU 102 can obtain the requested data from the system memory 106 using the PCI bus 108.
To provide faster access to particular peripheral device configurations, such as redundant array of independent disks (RAID) configurations, special motherboard configurations can be used. For example, FIG. 2 is a block diagram showing an exemplary conventional computer motherboard 150 having interrupt control logic. As above, the computer motherboard 150 includes a central processing unit (CPU) 102 in communication with a PCI bus 108. The PCI bus 108 is further in communication with a SCSI controller 104, system memory 106, and a RAID array 154 for persistent storage. In addition, the computer motherboard 150 includes a plurality of PCI slots 110 for PCI based cards.
The RAID array 154 is a collection of drives that collectively act as a single storage system, which can tolerate the failure of a drive without losing data, and can operate independently of each other. The RAID array 154 improves performance by disk striping, which interleaves bytes or groups of bytes across multiple drives, so more than one disk is reading and writing simultaneously. Mirroring or parity is used achieve fault tolerance. Mirroring is 100% duplication of the data on two drives and parity is used to calculate the data in two drives and store the results on a third. For example, a bit from drive 1 is XOR'd with a bit from drive 2, and the result bit is stored on drive 3. In addition, a failed drive can be hot swapped with a new one, and a related RAID firmware can automatically rebuild the lost data.
The computer motherboard 150 further includes an interrupt control circuit 152 that controls interrupt signals from the CPU 102, SCSI controller 104, and a RAID PCI slot 110′ via IRQ connections 114a, 114b, and 114c respectively. The RAID PCI slot 110′ is a PCI slot configured to allow communication between host adapter cards and the interrupt control circuit 152. Specifically, the RAID PCI slot 110′ is configured for use with a RAID host adapter card 156, which includes a RAID firmware 158 having an I/O processor (IOP). In use, the RAID host adapter card 156 is inserted into the RAID PCI slot 110′, which provides a link between the RAID firmware 158 and the interrupt control circuit via IRQ connection 114c. 
The interrupt control circuit 152 routes interrupts depending on the configuration. For example, in FIG. 2, the interrupt control circuit 152 reroutes the SCSI controller 104 interrupt from the CPU 102 to the RAID firmware 158. In this manner, the RAID firmware 158 can directly control the SCSI controller 104. For example, to read a file from the RAID array 154, the IOP of the RAID firmware 158 transmits an interrupt signal to the SCSI controller 104 via the interrupt control logic 152, and provides a read command to the SCSI controller 104 using the PCI bus 108. In response, the SCSI controller 104 transmits a command to the RAID array 154 to access the particular disk sectors. When the RAID array 154 reports back, the SCSI controller 104 uses direct memory access (DMA) circuitry to transfer the data on the RAID array 154 directly to the system memory 106. Once the transfer is complete, the SCSI controller 104 transmits an interrupt, indicating the data is in memory, which is rerouted by the interrupt control circuitry 152 to the IOP of the RAID firmware 158.
In addition to controlling interrupt signals, the interrupt control logic 152 also hides the SCSI controller 104 from the CPU 102. By hiding the SCSI controller 104 from the CPU 102, the interrupt control logic 152 allows the operating system executing on the CPU 102 to see only the IOP of the RAID firmware 158. Because operating systems often have problems processing information from two devices drivers for a single PCI device, the system performs better when only one IOP is presented to it.
For example, during a shutdown process, the operating system will find the driver for each PCI device and command it to shutdown its corresponding peripheral devices. When both the IOP of the RAID firmware 158 and the SCSI controller 104 are visible to the operating system, problems can occur. Specifically, the operating system will command the IOP of the RAID firmware 158 to shutdown. In response, the IOP of the RAID firmware 158 will command the SCSI controller 104 to shutdown. The operating system will also attempt to shutdown the SCSI controller 104. However, in the configuration of FIG. 2, the SCSI controller 104 will not have a corresponding driver, which will cause an error. Errors can also occur when the SCSI controller 104 does have a corresponding driver. In these circumstances, the operating system will attempt to update the boot disk prior to shutting the system down. However, the SCSI controller 104 will have already been shutdown by the IOP of the RAID Firmware 158. As a result, the operating system will not be able to update the boot disk, resulting in an error.
Thus, I/O chip hiding is important in system configurations such as that of FIG. 2. Unfortunately, not all motherboards include interrupt control circuitry 152 to hide multiple IOP devices. As a result, configurations such as that of FIG. 2 conventionally cannot be used on these types of motherboards.
In view of the foregoing, there is a need for systems and methods for I/O chip hiding of processor based controllers from operating systems. The methods should not require hardware changes, and should allow multiple IOP devices for a single peripheral device.